There are two basic techniques for implementing analog-to-digital converters (ADCs), the open-loop technique and the feedback technique. An open-loop converter generates a digital code directly upon application of an input voltage, and is generally asynchronous in operation. A feedback converter generates a sequence of digital codes from an input signal, reconverts these digital codes to an analog signal, and uses the reconverted analog signal as a feedback signal.
Sigma-delta ADCs use the feedback technique and have been known in the industry since the early 1960s. The sigma-delta technique is attractive because it achieves high resolution by precise timing instead of precisely matched on-chip components, such as resistors and capacitors used in open-loop converters. Thus, the sigma-delta technique is the technique of choice for many integrated circuit applications.
A basic sigma-delta ADC receives an analog input signal, and subtracts a feedback signal from the analog input signal to provide an error signal. The error signal is processed through a lowpass filter, and then quantized to form a digital output signal. A feedback digital-to-analog converter (DAC) provides the feedback signal after converting the digital output signal to analog form. Aside from the feedback DAC, the basic sigma-delta ADC may be implemented with conventional analog components such as operational amplifiers, comparators, and switched-capacitor filters. The basic sigma-delta ADC usually provides high resolution because integrated circuit clocking speeds allow the analog input signal to be highly over sampled. The basic sigma-delta ADC also has high signal-to-noise ratio (SNR) because the lowpass filter shapes quantization noise out-of-band, which can then be sufficiently attenuated by conventional filtering techniques.
One source of error degrading performance of sigma-delta ADCs is the degree of settling achieved in the switched-capacitor integrators. The degree of settling limits the clock rate of the converter. An upper bounded clock rate limits the maximum over-sampling ratio, or limits the maximum conversion bandwidth. If the necessary clock rate for a given over-sampling ratio and conversion bandwidth have been met, better inherent system settling may be traded off for such things as reduced gain-bandwidth of operational amplifiers, making the overall system smaller and more efficient. What is needed, then, is a sigma-delta ADC which exhibits better settling in the switched-capacitor circuitry resulting in a capability for higher over-sampling ratios, conversion bandwidths, or more efficient designs.